1. Field of the Invention
The present invention relates generally to a test circuit built into a certain circuit to be tested. In particular, the present invention relates to a linear feedback shift register, a multiple input signature register, and a built-in self test circuit using such registers.
The present application is based on Korea Patent Application No. 96-47171 which is incorporated herein by reference for all purposes.
2. Description of the Related Art
A built-in self test (BIST) circuit means a test circuit such as a test input applying circuit, an output-responsive discriminating circuit, etc., which is built into the target circuit to be tested such as a large scale integrated circuit (LSI), a printed circuit board, a device, etc. The BIST circuit enables the target circuit to be tested without using a separate tester or a test equipment.
According to one conventional method for implementing the BIST circuit, a test is created utilizing a random signal, the results of the circuit to be tested under the signal are compressed, and the finally compressed results are compared with one another. A linear feedback shift register (LFSR) and a multiple input signature register (MISR) have been primarily used to implement such a BIST circuit.
FIG. 1 is a schematic circuit diagram of a conventional LFSR. Referring to FIG. 1, the conventional LFSR includes storage elements 2, 4, . . . , 6, and 8 for storing coefficients Ci of a primitive polynomial, XOR gates 10, 12, . . . , 14, and 16 for XOR-gating the corresponding coefficient, stored data, and input data, and D-type flip-flops 20, 22, . . . , 24, and 26 for storing data of 1 bit, respectively.
The conventional LFSR of FIG. 1 is a circuit for creating a pseudo-random pattern, and performs the following primitive polynomial: EQU P=1+C.sub.1 X.sup.1 +C.sub.2 X.sup.2 + . . . +C.sub.n-1 X.sup.n-1 +C.sub.n X.sup.n Eq.( 1)
where C.sub.i denotes the coefficient of the respective terms of the above Eq. (1). If the coefficient of the term is `1`, a feedback path exists as shown in FIG. 1, while if the coefficient is `0`, no feedback path exists.
FIG. 2 is a schematic circuit diagram of a conventional MISR. Referring to FIG. 2, the conventional MISR includes storage elements 50, 52, . . . , 54, and 56 for storing coefficients of a primitive polynomial, XOR gates 30, 32, . . . , 34, and 36 for XOR-gating the corresponding coefficient, stored data, and input data, and D-type flip-flops 40,42, . . . , 44, and 46 for storing data of 1 bit.
The conventional MISR has a structure similar to the conventional LFSR of FIG. 1. But, unlike the LFSR of FIG. 1, the MISR of FIG. 2 receives and processes the data D1, D2, . . . , D.sub.n-1, and D.sub.n in parallel.
The number of flip-flops in the conventional LFSR of FIG. 1 is determined in accordance with the number of inputs of the circuit to be tested, while the number of flip-flops in the conventional MISR of FIG. 2 is determined in accordance with the number of outputs of the circuit to be tested. Since the number of flip-flops in the conventional BIST circuit, implemented using the LFSR and the MISR circuits of FIGS. 1 and 2, is dependant upon the number of inputs and outputs of the circuit to be tested, a circuit to be tested having a large number of inputs and outputs will require a corresponding large number of flip-flops on the LFSR and MISR test circuits. Consequently, the circuit real estate or overhead required for such a BIST circuit increases dramatically.
Accordingly, the need exists for an LFSR and/or MISR circuit which is implemented using a memory already existing in a circuit to be tested.